altera waveform editor

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY abc IS
PORT ( a , b: IN STD_LOGIC;
c: OUT STD_LOGIC);
END abc;

ARCHITECTURE behave OF abc IS
BEGIN
PROCESS (a , b)
BEGIN
c <=  a and b;
END PROCESS;
END behave;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY abc IS

PORT ( a , b: IN bit_vector(0 to 1);

c: OUT boolean);

END abc;

ARCHITECTURE behave OF abc IS

BEGIN

PROCESS (a , b)

BEGIN

c <=  (a >= b);

END PROCESS;

END behave;