altera modelsim

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY s_machine IS
PORT ( clk,reset : IN STD_LOGIC;
state_inputs : IN STD_LOGIC_VECTOR (0 TO 1);
comb_outputs : OUT STD_LOGIC_VECTOR (0 TO 1) );
END s_machine;

ARCHITECTURE behv OF s_machine IS
TYPE states IS (st0, st1, st2, st3); --定义states为枚举型数据类型
SIGNAL current_state, next_state: states;
BEGIN

REG: PROCESS (reset,clk) -- 时序逻辑进程
BEGIN
IF reset = '1' THEN
current_state <= st0; -- 异步复位
ELSIF clk='1' AND clk'EVENT THEN
current_state <= next_state; -- 当测到时钟上升沿时转换至下一状态
END IF;
END PROCESS; -- 由信号current_state将当前状态值带出此进程进入进程COM

COM: PROCESS(current_state, state_Inputs) -- 组合逻辑进程
BEGIN
CASE current_state IS -- 确定当前状态的状态值
WHEN st0 => comb_outputs <= "00"; -- 初始态译码输出"00"
IF state_inputs = "00" THEN --根据外部的状态控制输入"00"
next_state <= st0; --在下一时钟后进程REG的状态将维持为st0
ELSE
next_state <= st1; -- 否则在下一时钟后进程REG的状态将为st1
END IF;

WHEN st1 => comb_outputs <= "01";-- 对应状态st1的译码输出"01"
IF state_inputs = "00" THEN -- 根据外部的状态控制输入"00"
next_state <= st1; -- 在下一时钟后进程REG的状态将维持为st1
ELSE
next_state <= st2; -- 否则在下一时钟后进程REG的状态将为st2
END IF;

WHEN st2 => comb_outputs <= "10"; --以下依次类推
IF state_inputs = "11" THEN
next_state <= st2;
ELSE
next_state <= st3;
END IF;

WHEN st3 => comb_outputs <= "11";
IF state_inputs = "11" THEN
next_state <= st3;
ELSE
next_state <= st0; -- 否则在下一时钟后进程REG的状态返回st0
END IF;
END case;
END PROCESS; -- 由信号next_state将下一状态值带出此进程进入进程REG
END behv;

------------------------------------------------------------

-- VHDL Testbench for s_machine

-- 2014 3 18 15 25 4

-- Created by "EditVHDL"

-- "Copyright (c) 2002 Altium Limited"

------------------------------------------------------------

Library IEEE;

Use     IEEE.std_logic_1164.all;

Use     IEEE.std_logic_textio.all;

Use     STD.textio.all;

------------------------------------------------------------

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entity Tests_machine is

end Tests_machine;

------------------------------------------------------------

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architecture behave of Tests_machine is

    component s_machine

        port (

            clk: in std_logic;

            comb_outputs: out std_logic_vector(0 to 1);

            reset: in std_logic;

            state_inputs: in std_logic_vector(0 to 1)

        );

    end component;

    signal clk: std_logic;

    signal comb_outputs: std_logic_vector(0 to 1);

    signal reset: std_logic;

    signal state_inputs: std_logic_vector(0 to 1);

constant clk_period : time := 50 ns;

begin

    DUT:s_machine port map (

        clk => clk,

        comb_outputs => comb_outputs,

        reset => reset,

        state_inputs => state_inputs

    );

    STIMULUS0:process

    begin

        clk <= '0';

        wait for clk_period/2;  --for 0.5 ns signal is '0'.

        clk <= '1';

        wait for clk_period/2;  --for next 0.5 ns signal is '1'.

    end process;

 

STIMULUS1:process

    begin

    state_inputs <= "00";

    reset <= '0';

        wait for 15 ns;

        reset <='1';

        wait for clk_period;

 state_inputs <= "00";

 wait for clk_period;

 state_inputs <= "01";

 wait for clk_period;

 state_inputs <= "10";

 wait for clk_period;

 state_inputs <= "11";

 

    end process;

    

end architecture;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

use ieee.numeric_std.all;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ADDER4 IS

PORT ( a, b : IN INTEGER RANGE 0 TO 9;

c, d, e, f : OUT integer);

END ADDER4;

ARCHITECTURE one OF ADDER4 IS

BEGIN

c <= a / b;

d <= a mod b;

e <= a * b;

f <= a ** b;

END one;