altium create FPGA

project -> FPGA project -> add to project schematic -> FPGA generic lib, port plugin place part -> tools -> quiet annotate -> connect wire, buses, place bus entry, label bus net net[x..y], label ramification  net[z] -> project compile, error message -> project configuration manager -> add constraint -> view, device view, compile, synthesis, build, program -> place sheet symbol, tab name symbol, select sch file (file should be added to project first) -> place add sheet entry, io -> or -> design, create sheet symbol from sheet, select .vhd file (file should be added to project first)